This invention relates to a field effect transistor (namely, FET), and in particular, a hetero-structure FET (namely, HFET) having an AlGaAs layer which forms a schottky contact with a gate electrode and a manufacturing the same.
Recently, it has been studied to adopt a hetero-structure in order to achieve a high breakdown voltage and to reduce a gate leak in an high output GaAs FET.
Generally, one stage of recess or two stage of recesses are formed at a gate portion to increase the breakdown voltage and further to reduce a parasitic resistance.
For instance, suggestion has been made about the FET having the two stage of recesses in Japanese Unexamined Patent Publication No. Hei. 8-97237. In this conventional example, an AlGaAs layer is arranged so as to serve as an etching stopper for an n-type GaAs active layer. Consequently, variation of a recess depth can be reduced.
The above FET will be manufactured by the following steps. A first n-type GaAs active layer, a first AlGaAs stopper layer, a second n-type GaAs active layer, a second AlGaAs stopper layer and a third n-type GaAs active layer are sequentially deposited on a GaAs substrate by the use of the known epitaxial growth process. Subsequently, a source electrode and a drain electrode are formed on the third n-type GaAs active layer by the use of photo-lithography and lift-off process.
Thereafter, an etching (selective recess etching) is selectively carried out for the third n-type GaAs active layer to form a wide recess. In this event, the etching is stopped by the second AlGaAs stopper layer.
Successively, the etching is selectively carried out for the second n-type GaAs active layer to form a narrow recess. In this event, the etching is stopped by the first AlGaAs stopper layer.
Subsequently, a gate electrode is formed on the first AlGaAs stopper layer in the narrow recess by the use of the vapor lift-off method. In this event, the gate electrode forms a schottky contact with the first AlGaAs stopper layer. Consequently, the variation due to the process of the recess shape is reduced in the above-mentioned FET.
In such a HFET, when the concentration of the AlGsAs layer (the first AlGaAs stopper layer) which forms the schottky contact with the gate electrode is higher or 5xc3x971017 cm31 3, the transistor or the device may be destroyed by an increase of a current density, and the breakdown voltage may be also reduced. On the other hand, it has been generally noticed that an Al composition ratio should be effectively increased to enhance an etching selectivity during etching the GaAs layer.
According to experiments of inventors, as the Al composition ratio of the second AlGaAS stopper layer is increased on the condition that the impurity concentration is kept constant, a build up resistance Ron which appears in an I-V characteristic of the HFET is rapidly increased.
Consequently, even when the Al composition ratio is slightly varied during the epitaxial growth process of the AlGaAs layer, the characteristic of the HFET (in particular, the DC characteristic) is largely fluctuated. Further, the RF characteristic of the HFET is also fluctuated by the increase of the build up resistance Ron.
It is therefore an object of this invention to provide a field effect transistor (FET) which is capable of realizing uniform and excellent DC and RF characteristics by preventing a rapid increase of a build up resistance of the FET.
It is another object of this invention to provide a method of manufacturing a field effect transistor (FET) which is capable of achieving an excellent etching selectivity during etching a GaAs layer.
According to this invention, a field effect transistor has a preselected build up resistance with respect to an I-V characteristic of the transistor. In this event, a first GaAs layer is formed on a GaAs substrate. Further, an AlGaAs layer is formed on the first GaAs layer and has a predetermined impurity concentration and a preselected Al composition ratio. Moreover, a gate electrode is placed on the AlGaAs layer to form a schottky contact with the AlGaAs layer. In addition, a second GaAs layers are arranged on both sides of the gate electrode via a recess and are formed on said AlGaAs layer. Finally, source and drain electrodes are formed on the second GaAs layers.
With such a structure, the Al composition ratio is determined within a preselected range defined by a relationship between the impurity concentration and the built up resistance. Specifically, the Al composition ratio is determine in accordance with the impurity concentration so as to prevent the increase of the build up resistance.
More specifically, the preselected range falls between a first composition ratio and a second composition ratio. Herein, the first composition ratio is substantially equal to 0.1 while the second composition ratio is specified when the build up resistance rapidly rises as the Al composition ratio is gradually increased.
Moreover, the impurity concentration falls within the range between 1xc3x971016 cmxe2x88x923 and 5xc3x971017 cmxe2x88x923. In this case, the impurity concentration is set to higher than 1xc3x971016 cmxe2x88x923 so as to substantially control the impurity concentration of the an AlGaAs layer while the impurity concentration is set to less than 5xc3x971017 cmxe2x88x923 in order to prevent deterioration of said transistor.